Circuits typically are prone to defects introduced during a manufacturing process. To test for defects, a scan input may be applied to scan channels, clocks triggered and the result of the scan outputs from the scan channels may be analyzed. The test may include large numbers and variations of scan inputs being applied to scan channels of the circuit. Typically the tests take a great amount of time, produce large amounts of data for analysis, and require large amounts of resources for that analysis.
As Application Specific Integrated Circuit (ASIC) and Processor chips continue to get larger, test data volume and test time naturally increase as well. It continually becomes even more important to increase test efficiency. One method to increase efficiency is to deliver scan data in parallel to many parts of the chip at once, usually through a fan-out network feeding to many channels, which in turn feed a section of logic on the chip, and have that accompanied with a Multiple Input Signature Register (MISR) for on-chip data compression. This technique is called On Product Multiple Input Signature Register (OPMISR). This also includes a method for masking specific data in the channels, which can be used to prevent possible corruption of the MISR. This method for masking specific data in the channels including an OPMISR+ and OPMISR++ test versions were developed and are supported by Cadence Corporation.
Typically, OPMISR masking has two mask latches per MISR bit that are referred to as Channel Mask Scan Bits in Channel Mask Scan Registers (CMSRs) and two Channel Mask Enable (CME) signals. The CME signals decode to four states of: no masking, use mask bit 1, use mask bit 2, or mask all channels. The masking is applied as the data is unloaded from the channel into the MISR. When a bit position in a channel is going to shift into the MISR, the global CME signal is set to the desired mask state. For example, if channel 3 needs scan position 28 to be ignored, when bit 28 of the channel is about to be shifted into the MISR during the unload, the CME signals could be set to use mask register 1. The channel 3 mask scan bit in mask register 1 would have previously been set to mask. Other mask bits for other channels may or may not have been set to mask based on needs for the rest of the scan unload.
In large complex processors there can be more than one MISR. As used in the following description and claims, an OPMISR+ satellite includes one MISR and the channels above the MISR. With common Channel Mask Scan Registers (CMSRs) scanned into multiple OPMISR+ satellites and a global pair of Channel Mask Enable (CME) signals, typically there is over masking in OPMISR+ test patterns, which reduces the effectiveness of the patterns. It can be more practical to have several of these OPMISR+ satellites spread throughout the chip. For most efficient scanning and less scan data, the Channel Mask Scan Bits for register 0 and register 1 are scan initialized in parallel and shared across satellites. However, this means all satellites have the same mask bits. Additionally, typically all satellites get the same CME information during unload. For example, assume the first satellite needed bit 4 of the channel mask scan register set and used at the scan position 28 but the second satellite did not. With both satellites receiving the same data for the channel mask scan register the bit in the second satellite would unnecessarily be masked at the same time as the bit in the first mask register.
Thus, while it is efficient to share channel mask enable pins, one is left with the problem of over masking. All the channels with their mask bit set are masked whenever the CME signals indicates to use that masking, even if that bit position was needed to be masked on just one channel in just one satellite.